CMOS (Complimentary Metal Oxide Semiconductor) uses. Based on our model we develop heuristics to perform transistor sizing in CMOS layouts for minimizing power consumption while meeting given delay constraints. CMOS is a type of construction of an integrated circuit, with multiple transistors connected in a circuit. We extend our model to analyze power-delay characteristic of a CMOS circuit and derive the power-delay optimal size of a transistor. We derive analytical formulation for computing the power optimal size of a transistor and isolate the factor affecting the power optimal size. CMOS circuits are constructed so that all PMOS transistors must have either an input from the voltage source or from another PMOS transistor. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fan-out load should be enlarged to minimize the power consumption of the circuit. Experimental results (SPICE simulations) are presented to confirm the correctness of our analytical model.ĪB - We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our model we develop heuristics to perform transistor sizing in CMOS layouts for minimizing power consumption while meeting given delay constraints. We derive analytical formulation for computing the power optimal size of a transistor and isolate the factor affecting the power optimal size. N2 - We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. T1 - Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint In this work, the high-frequency performance of a 0.18-m CMOS device has been analyzed with various multi-finger layouts and biases to find the optimal.